1. Field of the Invention
The present invention relates to an ESD protection circuit, and more particularly relates to an ESD protection circuit that utilizes low voltage sensible components for being a releasing path of the ESD current.
2. Description of the Prior Art
Because of the minuteness of the circuit components and the improvement in precision of the electronic apparatus, the apparatus, the minute electric components inside especially are very sensitive and need protection against the static electricity that is induced by the working environment or touch of a user.
Therefore, most of the precise electric apparatus needs additional design of an ESD protection circuit for suitably releasing static electricity that may occur and protecting the electric components of the circuit in the apparatus against the damage of the high voltage induced by ESD.
An I-V graph of a typical stacked NMOS ESD protection circuit is illustrated in FIG. 1. Referring to FIG. 1, the horizontal coordinate is the voltage difference between the source and the drain and the vertical coordinate is the current of the drain. According to the graph, when the voltage difference between the source and the drain increases, the current of the drain increases correspondingly. After the voltage difference between the source and the drain exceeds a trigger voltage value, the punch through effect will occur that makes the voltage difference start to snap-back till the voltage difference decrease to a holding voltage value. The voltage difference range from the trigger voltage to the holding voltage is called snap-back region. Furthermore, after the voltage difference between the source and the drain decrease to the holding voltage, the voltage difference will increase smoothly, and the current of the drain will increase correspondingly.
Following the description above, when the static electricity voltage exceeds the trigger voltage value, the punch through effect will happen and result in electric conduction of the stacked NMOS as an ESD protection circuit, so the static electricity current is released to the ground through the stacked NMOS. Thus the electric components have been protected against the damage of ESD. However, there are disadvantages for the typical NMOS ESD protection circuit: If the static electricity voltage does not exceed the trigger voltage value, then the ESD protection circuit will not conduct electrically, i.e. the static electricity current will not be released and it will be constantly held in the electric apparatus. It is a instable factor and the user cannot predict when the electric apparatus will be seriously damaged.
A typical stacked NMOS ESD protection circuit in a IC is illustrated in FIG. 2. The object of the IC is to connect semiconductor chips or interfaces of a subsystem that work with different voltages. Therefore there is mixed-voltage inside the IC and the voltage values are Vdd and Vss respectively. Referring to FIG. 2, a I/O pad of the IC is connected to the inner circuit and the drain of the first NMOS (N1), the gate of N1 is connected to the power supply Vdd, the source of N1 is connected to the drain of the second NMOS (N2), the gate of N2 is connected to the power supply Vss and the source of N2 is connected to the ground.
Still referring to FIG. 2, N1 and N2 are connected with cascade configuration and the nodes between them become a common diffusion region as there is a parasite lateral NPN bipolar transistor existed inside the stacked NMOS. When the static electricity voltage exceeds the trigger voltage value, the lateral NPN bipolar transistor will conduct electrically and the static electricity current can be released from the inner circuit. However referring to FIG. 1, if the static electricity voltage does not exceed the trigger voltage value, then the lateral NPN bipolar transistor will not conduct electrically, the static electricity current will not be released and it will be constantly held in the IC. And because the breakdown voltage of the MOS gate oxide decrease in a mixed voltage I/O circuit, finally the static electricity current held in the IC will result in damage of the MOS gate oxide that belongs to the I/O buffer inside the I/O pad.
Considering in a typical ESD protection circuit of above description, when the static electricity exists in the circuit but does not exceed the trigger voltage, the protection circuit will not be active. Thus a protection circuit that is more sensitive to detect and release static electricity is needed for releasing the static electricity that does not exceed the trigger voltage and protecting the components inside the circuit against damage.